Showing posts with label placement. Show all posts
Showing posts with label placement. Show all posts

Sunday, October 10, 2010

Lattice XP2 Brevia Diamond Starter Project

Its a royal PITA to specify the pinout of a 144 pin part! So there is no point to doing this more than once -- across the entire internet.

Its unfortunate that Lattice does not provide one, but their Demo project does not specify the IOs since they are not used.

In my code repository is a Diamond project that specifies all XP2 IOs as used by the Brevia board. And it sets the XP2 part up with 3 clocks, 400mhz, 50mhz, and 25mhz. Of course you can change these clock values by editing the "pll" module.

You checkout the entire project (recommended), or browse and pull down the key files to add into your own project:

top.v: the "main" verilog file

starter1.lpf: the file that places the verilog symbols onto particular pins

pll.v: autogenerated pll module that sets up the 3 clocks.